The present invention relates to an electronic device which is integrated in a semiconductor substrate. More particularly, it relates to a structure of an electronic device that can be integrated monolithically in a semiconductor, e.g., a FET (Field-Effect Transistor).
The invention further relates to an integrated memory circuit comprising a plurality of such transistors. The invention is directed to increase the number of memory cells that are integrated in the semiconductor material, and improve the quality of the information that is stored in the memory.
Current technologies for fabricating semiconductor integrated devices have led to a large reduction in the circuit area requirements of individual electronic devices. In the case of a FET, this is achieved by progressively reducing the size of the FET active areas that compose the basic blocks of most electronic circuits. Sub-micron size (e.g., 0.18-micron) transistors can be currently obtained, and the scaling-down trend shows no signs that it may end there with the integration process.
All types of semiconductor circuits have benefited from the intensified integration, and especially so integrated memory circuits having non-volatile memory cells, such as EPROM, EEPROM and Flash-EEPROM cells, integrated therein.
There are two types of non-volatile memories which are comprised of floating-gate transistors. The first type is represented by EPROMs and can be programmed electrically and erased optically.
The second type, represented by EEPROMs and Flash-EEPROMs, allows the stored information to be modified electrically for both writing and erasing.
In either cases, the information is recorded in the memory in the form of electric charges that are stored into the floating gates of the transistors.
EEPROMs will be specifically considered here, in which the state of any memory cell, or of the floating-gate transistor comprising the cell, can be altered by causing electrons to flow through a thin layer of silicon oxide by tunnel effect.
It is well known to the skilled persons in the art that EEPROMs exist in two main types, i.e., one type having a single polysilicon level provided to form the floating gate region, and another type having two discrete polysilicon levels provided to also form a control gate region. This distinction is, however, irrelevant to this invention.
The individual non-volatile EEPROM cell comprises a FET or a MOSFET transistor having a drain region and a source region. These regions are integrated in a semiconductor substrate and isolated from each other by a substrate portion known as the channel region. A floating gate region is formed above the substrate and is separated from the latter by a thin layer of a dielectric oxide known as the tunnel oxide.
When the conduction channel of the floating-gate transistor is put in a saturated state, the agitation of the hot carriers (consisting of electrons when the channel is of the N type) releases sufficient energy for them to flow past the barrier formed by the tunnel oxide between the conduction channel and the floating gate. The hot carriers then become trapped within the floating gate.
With a sufficiently high program voltage, the electrons trapped in the floating gate will be unable to leave it, although they keep being agitated. However, this agitation produces inadequate energy for them to get out of the floating gate. As a result, these electrons block the conduction channel with an electric field.
To erase the cell, a high voltage is applied to the drains and sources of the floating-gate transistors, with the floating gate held at a zero potential. Under such conditions, a powerful reverse electric field is created in the transistor, which causes the trapped carriers to migrate toward the drain or the source electrode.
It can be appreciated from the foregoing that, for the purpose of an intensified integration, any reduction in size of these memory cells goes forcibly through a reduction of the coupling surfaces between the floating gates and the conduction channels of the floating-gate transistors. This reduction of the coupling surfaces alters the conditions for conduction by the transistor channel so deeply that the thickness of the tunnel oxide also has to be reduced, down to less than 80 xc3x85ngstrxc3x6ms (1 xc3x85ngstrxc3x6m=0.1 nm).
The thickness of the tunnel oxide turns out to be very difficult to reduce for two reasons. On the onehand, with the decrease of thickness, fault density is bound to increase and the rate of product acceptance decrease. On the otherhand, charge (or electron) retention in the floating gates diminishes with reduction in thickness.
In(reality?), due to their agitation, the electrons do flow at least to some degree past the barrier created by the thick gate oxide. As a result, the information stored in a memory location will vanish gradually. It is presently estimated to practically disappear over a 10-year period. If the tunnel oxide were provided at a thinner dimension, this retention time would be greatly shortened.
In order to reduce the dimension of the thin layer of tunnel oxide while retaining its primary dielectric function, other migrating mechanism has been considered whereby the electrons flow along a conduction path other than the dielectric oxide barrier, and become trapped in the floating gate region. For example, as pointed out by D. I. Gittins et al., Nature, 11.02.2000, vol. 408, pages 67-69, there exist organic molecules that contain redox centers, i.e., chemical species whose oxidation number (and hence, electron structure) can be modified reversibly. These molecules support a so-called resonant tunneling, and perform promisingly when provided as molecular layers between electric contacts. However, their integration to more complex structures still poses some problems.
Exemplary of such molecules are compounds that contain a reversibly reducible bipyridinium group centrally located, e.g., N,N-di-(10-mercaptodecyl)-4,4xe2x80x2-bipyridinium dibromide.
These compounds usually contain terminal thiol-groups in order for them to become bonded to the gold of electrodes used for electrical measuring purposes.
Since it would be extremely difficult to provide gold electrodes in the form of parallel plates spaced one molecule-length (approximately 3 nm) apart, the above molecules are tested by bonding them with one end to one electrode and with the other end to a gold nano-particle (measuring about 6 nm in diameter) that, in turn, is used as a contact of a scanning tunnelling microscope operated in an electric-probe mode.
While the above-outlined arrangement is useful as far as determining the electrical characteristics of the molecules and controlling the conduction mechanisms and paths (tunneling, resonant tunneling, etc.) is concerned, it is incompatible with silicon-integrated circuits.
Accordingly, there exists in the art a need for methods of integrating molecular layers to conventional silicon-based microelectronic structures and enabling them to function as carriers of electrically charged particles. The present invention satisfies this need and provides further related advantages.
One aspect of the present invention is to provide a hybrid configuration in which organic molecules are bonded to conventional silicon-based microelectronic structures and enabling them to function as carriers of electrically charged particles. It was found that the basic component of nearly all integrated electronic circuits, i.e., the MOS or the MOSFET transistor, would meet the requirement of receiving said molecules.
In one embodiment, the present invention is related to a method of controlling and modulating the charge flow through a dielectric oxide of a MOS transistor, wherein the transistor structure comprises a layer of silicon oxide (gate oxide) formed between two silicon plates, with the plates overhanging the silicon oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape and a height of about 3 nm, said method comprising the steps of:
chemically altering the surfaces of said silicon plates to have different functional groups in said undercut from those in the remainder of the surfaces; and
selectively reacting said functional groups located at the undercut with an organic molecule so as to establish a covalent bond to each of the molecule ends, said molecule containing a reversibly reducible center and having a molecular length of about 3 nm.
said organic molecule has the formula R1xe2x80x94Yxe2x80x94R1,
wherein,
Y is a redox center having the following formula: 
xe2x80x83R1 is a xe2x80x94CH2xe2x80x94(CHR2)nxe2x80x94R3 chain, wherein n=6-8;
R2 is H or C1-C6alkyl group;
R3 is selected from a group consisting of xe2x80x94CH2xe2x80x94CH2xe2x80x94X, xe2x80x94CHxe2x95x90CH2, xe2x80x94Cxe2x89xa1CH, and Cxe2x89xa1N, wherein X is either xe2x80x94SH or xe2x80x94SiH2Cl; and Zxe2x88x92 is a monovalent anion.
In another embodiment, the instant invention is related to a transistor structure comprising a layer of dielectric silicon oxide formed between two silicon plates, wherein said plates overhang said oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape and a preset height, and wherein the surfaces of said plates at said undercut have different functional groups from those in the other surfaces.
The features and advantages of the method according to the invention will be apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.